RTP MEME4D One of the goals of the RISC chip design concept was to remove these variants so that the pipeline logic was simplified, which leads to the classic RISC pipeline which completes one instruction every cycle. Branch delay slots are found mainly in DSP architectures and older RISC architectures. However, there is one problem that comes up in pipeline systems that can slow performance. The processor's pipeline will normally have already read the next instruction, the write, by the time the ALU has calculated which path it will take.|Broadcasting & Cable. Cahners Business Information